This invention relates generally to a circuit for arbitrating between two bus systems and, more specifically, to controlling the writing by one bus system to a second bus system.
Different arbitration schemes exist for coordinating the transfer of data from a first bus system to a second bus system. Such arbitration schemes must insure that the write data bus does not overwrite previously written data and that the read data bus only reads valid data. In order to prevent the write data bus from overwriting previous data, traditional arbitration schemes sometimes use handshaking control signals to regulate the write operations.
Another traditional arbitration scheme uses a control signal to force the write bus system to suspend a write operation. Where the write bus system is controlled by a microprocessor, this suspension of the microprocessor is achieved by using "wait states." The read bus system can be controlled in a similar manner by using either handshaking signals or suspension of processing to prevent the read data bus from receiving invalid data.
However, each of the above arbitration schemes has a drawback in that the maximum number of bus operations possible per second for each bus system is decreased due to the delay in either acknowledging the handshake control signal or in the suspension of the processor by forced wait states. In most bus systems, such bus efficiency degradation is acceptable as a design trade-off toward achieving data integrity.
However, in data systems where some data losses are acceptable, it is preferable to maintain the highest bus operation rate possible. For example, in digitized voice data transmissions less than 100% data integrity will be acceptable because a sample lost will only mean a slight, often undetectable, degrading of the voice quality. If desired, processing techniques such as interpolation can be used to compensate for the error. Similarly, the transmission of digitized pictures for human viewing will have a certain allowable data loss. Another example would be in communications systems where error detection and correction is built in, as by using coding schemes or providing for the retransmission of a message in error.
In such data systems, an arbitration scheme need not be concerned with delaying the writing or reading of data in an attempt to ensure 100% data integrity. It is therefore an objective of this invention to provide an arbitration scheme that allows a first data bus to write to a second data bus without delaying the operation of the writing data bus. A second objective of the invention is to make known to the reading data bus when a data overrun condition occurs, so that corrective measures can be taken. A third objective is to implement the arbitration scheme in a cost effective and efficient electronic circuit.